Renesas R5S72623 Manual Do Utilizador

 

Section 2   CPU 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 61 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Register indirect 
with 
displacement 

@(disp:4, 

Rn)

The effective address is the sum of Rn and a 4-bit  
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte 
operation, is doubled for a word operation, and is 
quadrupled for a longword operation. 

Rn

Rn + disp 

× 1/2/4

+

×

1/2/4

disp

(zero-extended)

Byte:  
Rn + disp  

Word:  
Rn + disp 

 2 

Longword:  
Rn + disp 

 4 

Register indirect 
with 
displacement 

@(disp:12,

Rn)

The effective address is the sum of Rn and a 12-
bit  
displacement (disp). The value of disp is zero-
extended. 

+

Rn

disp

(zero-extended)

Rn + disp

Byte:  
Rn + disp  

Word:  
Rn + disp  

Longword:  
Rn + disp 

Indexed register 
indirect 

@(R0,Rn)

The effective address is the sum of Rn and R0. 

Rn

R0

Rn + R0

+

Rn + R0 

GBR indirect 
with 
displacement 

@(disp:8, 

GBR)

The effective address is the sum of GBR value 
and an 8-bit displacement (disp). The value of 
disp is zero-extended, and remains unchanged for 
a byte operation, is doubled for a word operation, 
and is quadrupled for a longword operation. 

GBR

1/2/4

GBR

+ disp 

× 1/2/4

+

×

disp

(zero-extended)

Byte:  
GBR + disp 

Word:  
GBR + disp 

 2

Longword: 
GBR + disp 

 4