Renesas R5S72623 Manual Do Utilizador
Section 20 Controller Area Network
Page 1022 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit 4 - Receive Error Counter Warning Interrupt Flag (IRR4): This bit becomes set if the
receive error counter (REC) reaches a value greater than 95 when this module is not in the Bus Off
status. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect.
receive error counter (REC) reaches a value greater than 95 when this module is not in the Bus Off
status. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect.
Bit 4: IRR4
Description
0 [Clearing
condition]
Writing 1 (Initial value)
1
Error warning state caused by receive error
[Setting condition] When REC
96 and this module is not in Bus Off
Bit 3 - Transmit Error Counter Warning Interrupt Flag (IRR3): This bit becomes set if the
transmit error counter (TEC) reaches a value greater than 95. The interrupt is reset by writing a '1'
to this bit position, writing '0' has no effect.
transmit error counter (TEC) reaches a value greater than 95. The interrupt is reset by writing a '1'
to this bit position, writing '0' has no effect.
Bit 3: IRR3
Description
0 [Clearing
condition]
Writing 1 (Initial value)
1
Error warning state caused by transmit error
[Setting condition] When TEC
96
Bit 2 - Remote Frame Receive Interrupt Flag (IRR2): Flag indicating that a remote frame has
been received in a mailbox. This bit is set if at least one receive mailbox, with related MBIMR not
set, contains a remote frame transmission request. This bit is automatically cleared when all bits in
the Remote Frame Receive Pending Register (RFPR), are cleared. It is also cleared by writing a '1'
to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
been received in a mailbox. This bit is set if at least one receive mailbox, with related MBIMR not
set, contains a remote frame transmission request. This bit is automatically cleared when all bits in
the Remote Frame Receive Pending Register (RFPR), are cleared. It is also cleared by writing a '1'
to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
Bit 2: IRR2
Description
0
[Clearing condition] Clearing of all bits in RFPR (Initial value)
1
At least one remote request is pending
[Setting condition]
When remote frame is received and the corresponding MBIMR = 0
Bit 1 – Data Frame Received Interrupt Flag (IRR1): IRR1 indicates that there are pending Data
Frames received. If this bit is set at least one receive mailbox contains a pending message. This bit
is cleared when all bits in the Data Frame Receive Pending Register (RXPR) are cleared, i.e. there
is no pending message in any receiving mailbox. It is in effect a logical OR of the RXPR flags
from each configured receive mailbox with related MBIMR not set. It is also cleared by writing a
'1' to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
Frames received. If this bit is set at least one receive mailbox contains a pending message. This bit
is cleared when all bits in the Data Frame Receive Pending Register (RXPR) are cleared, i.e. there
is no pending message in any receiving mailbox. It is in effect a logical OR of the RXPR flags
from each configured receive mailbox with related MBIMR not set. It is also cleared by writing a
'1' to all the correspondent bit position in MBIMR. Writing to this bit has no effect.