Renesas R5S72623 Manual Do Utilizador

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Section 21   IEBus
TM
 Controller 
R01UH0134EJ0400  Rev. 4.00  
 
Page 1129 of 2108 
Sep 24, 2014 
 
 
 
SH7262 Group, SH7264 Group 
Bit Bit 
Name 
Initial 
Value R/W 
Description 
2 RXERTME 
R/(W)* 
Receive Timing Error 
Set to 1 if data is not received at the time specified by 
the IEBus protocol during data reception. This module 
sets this bit and enters the wait state. This flag is 
enabled only after the receive start flag (RXS) is set. If 
this error occurs before the receive start flag (RXS) is 
set, this module stops communication and enters the 
wait state. This bit is not set in this case. 
[Setting condition] 
  When a timing error occurs during data reception 
[Clearing condition] 
  When 1 is written 
1 RXEDLE 
R/(W)* 
Overflow of Maximum Number of Receive Bytes in One 
Frame 
Indicates that the data reception has not finished within 
the maximum number of bytes defined by the 
communications mode because of a parity error or 
overrun error causing the retransfer of data, or that 
reception has not been completed because the 
message length value exceeds the maximum number 
of receive bytes in one frame. This module sets the 
RXEDLE flag and enters the wait state. This flag is 
enabled only after the receive start flag (RXS) is set. If 
this error occurs before the receive start flag is set, this 
module stops communication and enters the wait state. 
This bit is not set in this case. 
[Setting condition] 
  When the reception has not been completed within 
the maximum number of bytes defined by 
communications mode. 
[Clearing condition] 
  When 1 is written