Renesas R5S72623 Manual Do Utilizador
Section 33 Power-Down Modes
Page 1816 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
When deep standby mode is canceled by interrupts (NMI or realtime clock alarm) or changes on
the pins for canceling, the deep standby cancel source flag register (DSFR) can be used to confirm
which source has canceled the mode.
the pins for canceling, the deep standby cancel source flag register (DSFR) can be used to confirm
which source has canceled the mode.
Pins retain the state immediately before the transition to deep standby mode. However, in system
activation through the external memory, the retention of the states of the external memory control
pins is cancelled so that programs can be fetched after cancellation of deep standby mode. Other
pins, after cancellation of deep standby mode, continue to retain the pin states until writing 0 to the
IOKEEP bit in DSFR after reading 1 from the same bit. In system activation from the on-chip
data-retention RAM, after cancellation of deep standby mode, both the external memory control
pins and other pins continues to retain the pin states until writing 0 to the IOKEEP bit in DSFR
after reading 1 from the same bit. Reconfiguration of peripheral functions is required to return to
the previous state of deep standby mode. Peripheral functions include all functions such as the
clock pulse generator, interrupt controller, general I/O ports, and peripheral modules. After the
reconfiguration, the retention of the pin state can be canceled and the LSI returns to the state prior
to the transition to deep standby mode by reading 1 from the IOKEEP bit in DSFR and then
writing 0 to it.
activation through the external memory, the retention of the states of the external memory control
pins is cancelled so that programs can be fetched after cancellation of deep standby mode. Other
pins, after cancellation of deep standby mode, continue to retain the pin states until writing 0 to the
IOKEEP bit in DSFR after reading 1 from the same bit. In system activation from the on-chip
data-retention RAM, after cancellation of deep standby mode, both the external memory control
pins and other pins continues to retain the pin states until writing 0 to the IOKEEP bit in DSFR
after reading 1 from the same bit. Reconfiguration of peripheral functions is required to return to
the previous state of deep standby mode. Peripheral functions include all functions such as the
clock pulse generator, interrupt controller, general I/O ports, and peripheral modules. After the
reconfiguration, the retention of the pin state can be canceled and the LSI returns to the state prior
to the transition to deep standby mode by reading 1 from the IOKEEP bit in DSFR and then
writing 0 to it.
(4) Notes on Transition to Deep Standby Mode
If multiple canceling sources have been specified and multiple canceling sources are input,
multiple cancel source flags will be set.
multiple cancel source flags will be set.