Renesas R5S72623 Manual Do Utilizador
Section 10 Direct Memory Access Controller
Page 414 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
CHCR DMARS
DMA
Transfer
Request
Source
Source
DMA Transfer Request Signal
Transfer
Source
Source
Transfer
Destination
Destination
Bus
Mode
Mode
RS[3:0] MID
RID
1000 010001
01
Sampling
rate
converter
Channel 1
Channel 1
IDEI1 (input data empty)
Any
SRCIDR_1 Cycle
steal
10
ODFI1 (output data full)
SRCODR_1 Any
010100 01 Renesas serial
peripheral
interface
Channel 0
interface
Channel 0
SPTI0 (transmit buffer empty)
Any
SPDR_0
10
SPRI0 (receive buffer full)
SPDR_0
Any
010101 01 Renesas serial
peripheral
interface
Channel 1
interface
Channel 1
SPTI1 (transmit buffer empty)
Any
SPDR_1
10
SPRI1 (receive buffer full)
SPDR_1
Any
011000 01 I
2
C bus interface
3
Channel 0
Channel 0
TXI0 (transmit data empty)
Any
ICDRT_0
10
RXI0 (receive data full)
ICDRR_0
Any
011001 01 I
2
C bus interface
3
Channel 1
Channel 1
TXI1 (transmit data empty)
Any
ICDRT_1
10
RXI1 (receive data full)
ICDRR_1
Any
011010 01 I
2
C bus interface
3
Channel 2
Channel 2
TXI2 (transmit data empty)
Any
ICDRT_2
10
RXI2 (receive data full)
ICDRR_2
Any
011100 11 CD-ROM
decoder
IREADY (decode end)
STRMDOUT Any
Cycle
steal or
burst
steal or
burst
100000 01 Serial
communication
interface with
FIFO
Channel 0
interface with
FIFO
Channel 0
TXI0 (transmit FIFO data empty) Any
SCFTDR_0 Cycle
steal
10
RXI0 (receive FIFO data full)
SCFRDR_0 Any
100001 01 Serial
communication
interface with
FIFO
Channel 1
interface with
FIFO
Channel 1
TXI1 (transmit FIFO data empty) Any
SCFTDR_1
10
RXI1 (receive FIFO data full)
SCFRDR_1 Any
100010 01 Serial
communication
interface with
FIFO
Channel 2
interface with
FIFO
Channel 2
TXI2 (transmit FIFO data empty) Any
SCFTDR_2
10
RXI2 (receive FIFO data full)
SCFRDR_2 Any