Renesas R5S72623 Manual Do Utilizador

 

 

Section 10   Direct Memory Access Controller 
 

Page 418 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

In dual address mode, both the transfer source and destination are accessed (selected) by an 
address. The transfer source and destination can be located externally or internally. 

DMA transfer requires two bus cycles because data is read from the transfer source in a data read 
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is 
temporarily stored in this module. In the transfer between external memories as shown in figure 
10.3, data is read to this module from one external memory in a data read cycle, and then that data 
is written to the other external memory in a data write cycle. 

Memory

Transfer source  

module

Transfer destination 

module

SAR

DAR

Data 
buffer

Memory

Transfer source  

module

Transfer destination 

module

SAR

DAR

Data 
buffer

Direct memory access  

controller

Direct memory access  

controller

The SAR value is an address, data is read from the transfer source module, 
and the data is temporarily  stored in the direct memory access controller.

First bus cycle

The DAR value is an address and the value stored in the data buffer in the
direct memory access controller is written to the transfer destination module. 

Second bus cycle

Data bus

Address bus

Data bus

Address bus