Renesas R5S72623 Manual Do Utilizador

 

 

Section 11   Multi-Function Timer Pulse Unit 2 
 

Page 496 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

5 

N 

0 

R/W 

Reverse Phase Output (N) Control 

This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while 
the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are 
output. 

0: Level output 

1: Reset synchronized PWM/complementary PWM 

output 

4 

P 

0 

R/W 

Positive Phase Output (P) Control 

This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while 
the positive pin (TIOC3B, TIOC4A, and TIOC4B) are 
output. 

0: Level output 

1: Reset synchronized PWM/complementary PWM 

output 

3 

FB 

0 

R/W 

External Feedback Signal Enable 

This bit selects whether the switching of the output of 
the positive/reverse phase is carried out automatically 
with channel-0 TGRA, TGRB, TGRC input capture 
signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 

0: Output switching is external input (Input sources are 

channel 0 TGRA, TGRB, TGRC input capture signal) 

1: Output switching is carried out by software (setting 

values of UF, VF, and WF in TGCR). 

2 

WF 

0 

R/W 

Output Phase Switch 2 to 0 

These bits set the positive phase/negative phase output 
phase on or off state. The setting of these bits is valid 
only when the FB bit in this register is set to 1.  In this 
case, the setting of bits 2 to 0 is a substitute for external 
input. See table 11.37. 

1 VF 

0  R/W 

0 UF 

0  R/W