Renesas R5S72623 Manual Do Utilizador

 

Section 2   CPU 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 51 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

31 to 15 

 All 

0  R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

14 BO  0 

R/W 

BO 

Bit 

Indicates that a register bank has overflowed. 

13 CS  0 

R/W 

CS 

Bit 

Indicates that, in CLIP instruction execution, the value 
has exceeded the saturation upper-limit value or 
fallen below the saturation lower-limit value. 

12 to 10 

 All 

0  R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

9 M 

 R/W 

M 

Bit 

Q Bit 

Used by the DIV0S, DIV0U, and DIV1 instructions. 

8 Q 

 R/W 

7 to 4 

I[3:0] 

1111 

R/W 

Interrupt Mask Level 

3, 2 

 All 

0  R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

1 S 

 R/W 

S 

Bit 

Specifies a saturation operation for a MAC 
instruction. 

0 T 

 R/W 

T 

Bit 

True/false condition or carry/borrow bit 

 

GBR is referenced as the base address in a GBR-referencing MOV instruction. 

VBR is referenced as the branch destination base address in the event of an exception or an 
interrupt. 

TBR is referenced as the start address of a function table located in memory in a 
JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.