Renesas R5S72622 Manual Do Utilizador

 

Section 20   Controller Area Network 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1023 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

0 

[Clearing condition] Clearing of all bits in RXPR (Initial value) 

1 

Data frame received and stored in Mailbox 

[Setting condition] When data is received and the corresponding MBIMR = 0

 

Bit 0 – Reset/Halt/Sleep Interrupt Flag (IRR0): This flag can get set for three different reasons. 
It can indicate that:  

1.  Reset mode has been entered after a SW (MCR0) or HW reset 

2.  Halt mode has been entered after a Halt request (MCR1) 

3.  Sleep mode has been entered after a sleep request (MCR5) has been made while in Halt mode. 
 
The GSR may be read after this bit is set to determine which state this module is in.  

Important: When a Sleep mode request needs to be made, the Halt mode must be used 
beforehand. Please refer to the MCR5 description and Figure 20.15 Halt Mode/Sleep Mode. 

IRR0 is set by the transition from "0" to "1" of GSR3 or GSR4 or by transition from Halt mode to 
Sleep mode. So, IRR0 is not set if this module enters Halt mode again right after exiting from Halt 
mode, without GSR4 being cleared. Similarly, IRR0 is not set by direct transition from Sleep 
mode to Halt Request. At the transition from Halt/Sleep mode to Transition/Reception, clearing 
GSR4 needs (one-bit time - TSEG2) to (one-bit time * 2 - TSEG2).  

In the case of Reset mode, IRR0 is set, however, the interrupt to the CPU is not asserted since 
IMR0 is automatically set by initialisation. 

0 [Clearing 

condition] 

Writing 1 

1 

Transition to S/W reset mode or transition to halt mode or transition to sleep 
mode (Initial value) 

[Setting condition] 

When reset/halt/sleep transition is completed after a reset (MCR0 or HW) or 
Halt mode (MCR1) or Sleep mode (MCR5) is requested