Renesas R5S72622 Manual Do Utilizador
Section 20 Controller Area Network
Page 1036 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit 15 to 0 — Remote Request pending flags for mailboxes 31 to 16 respectively.
Bit[15:0]: RFPR1
Description
0 [Clearing
Condition]
Writing '1' (Initial value)
1 Corresponding
Mailbox received Remote Frame
[Setting Condition]
Completion of remote frame receive in corresponding mailbox
Completion of remote frame receive in corresponding mailbox
RFPR0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
RFPR0[15:0]
Note: * Only when writing a '1' to clear.
Bit 15 to 0 — Remote Request pending flags for mailboxes 15 to 0 respectively.
Bit[15:0]: RFPR0
Description
0 [Clearing
Condition]
Writing '1' (Initial value)
1 Corresponding
Mailbox received Remote Frame
[Setting Condition]
Completion of remote frame receive in corresponding mailbox
Completion of remote frame receive in corresponding mailbox
(7) Mailbox Interrupt Mask Register (MBIMR)
The MBIMR1 and MBIMR0 are 16-bit read/write registers. The MBIMR only prevents the setting
of IRR related to the Mailbox activities, that are IRR[1] – Data Frame Received Interrupt, IRR[2]
– Remote Frame Receive Interrupt, IRR[8] – Mailbox Empty Interrupt, and IRR[9] – Message
OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the corresponding
bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and IRR[9]) but
does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR. Similarly
when a mailbox has been configured for transmission, a mask prevents the generation of an
Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or
abortion of transmission (IRR[8]), however, it does not prevent this module from clearing the
corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does
not prevent this module from clearing the corresponding TXPR/TXCR bit + setting the ABACK
bit for abortion of the transmission.
of IRR related to the Mailbox activities, that are IRR[1] – Data Frame Received Interrupt, IRR[2]
– Remote Frame Receive Interrupt, IRR[8] – Mailbox Empty Interrupt, and IRR[9] – Message
OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the corresponding
bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and IRR[9]) but
does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR. Similarly
when a mailbox has been configured for transmission, a mask prevents the generation of an
Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or
abortion of transmission (IRR[8]), however, it does not prevent this module from clearing the
corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does
not prevent this module from clearing the corresponding TXPR/TXCR bit + setting the ABACK
bit for abortion of the transmission.