Renesas R5S72622 Manual Do Utilizador
Section 24 A/D Converter
Page 1274 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
6. The ADST bit is not cleared automatically, so steps 2. to 4. are repeated as long as the ADST
bit remains set to 1. When steps 2. to 4. are repeated, the ADF flag is kept to 1. When the
ADST bit is cleared to 0, A/D conversion stops. The ADF bit is cleared by reading ADF while
ADF = 1, then writing 0 to the ADF bit.
ADST bit is cleared to 0, A/D conversion stops. The ADF bit is cleared by reading ADF while
ADF = 1, then writing 0 to the ADF bit.
If both the ADF flag and ADIE bit are set to 1 while steps 2. to 4. are repeated, an ADI interrupt is
requested at all times. To generate an interrupt on completing conversion of the third channel,
clear the ADF bit to 0 after an interrupt is requested.