Renesas R5S72622 Manual Do Utilizador
Section 26 USB 2.0 Host/Function Module
Page 1408 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
14 CRCE
0
R/W* Receive
Data
Error
Indicates whether a CRC error or bit stuffing error
has been detected in the pipe during isochronous
transfer. Simultaneously with error detection, the
internal NRDY interrupt request is generated. For
details, see section 26.4.2, Interrupt Functions.
has been detected in the pipe during isochronous
transfer. Simultaneously with error detection, the
internal NRDY interrupt request is generated. For
details, see section 26.4.2, Interrupt Functions.
0: No error
1: An error occurred
13 to 11
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
10 to 0
FRNM[10:0]
H'000 R
Frame
Number
This module sets these bits to indicate the latest
frame number, which is updated every time an SOF
packet is issued or received (every 1 ms)
frame number, which is updated every time an SOF
packet is issued or received (every 1 ms)
Read these bits twice to check that the same value is
read.
read.
Note: * Only 0 can be written