Renesas R5S72622 Manual Do Utilizador

 
Section 26   USB 2.0 Host/Function Module 

Page 1526 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

Data transfers corresponding to USB requests that have been received should be done using the 
DCP. Before accessing the DCP buffer memory, the access direction should be specified using the 
ISEL bit in CFIFOSEL. 

A transaction is executed by setting the PID bits in the DCPCTR register to BUF. The BRDY 
interrupt or the BEMP interrupt can be used to detect the end of data transfer. Use the BRDY 
interrupt to detect the end of control write transfers and the BEMP interrupt to detect the end of 
control read transfers. 

With control write transfers during high-speed operation, the NYET handshake response is carried 
out based on the state of the buffer memory. 

Control transfers are terminated by setting the CCPL bit to 1 with the PID bit in DCPCTR set to 
PID = BUF. 

After the above settings have been entered, this module automatically executes the status stage in 
accordance with the data transfer direction determined at the setup stage. The specific procedure is 
as follows. 

(i) 

For control read transfers: 

This module receives a zero-length packet from the USB host and sends an ACK response. 

(ii) 

For control write transfers and no-data control transfers: 

This module sends the zero-length packet from the USB host and receives an ACK response.