Renesas R5S72622 Manual Do Utilizador

 

Section 27   Video Display Controller 3 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1551 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

DV_VSYNC
DV_HSYNC

DV_CLK

DV_DATA7 to
DV_DATA0

Vsync
Hsync
Video [7:0]
dv_clk

IV1-BUS (write)

IV2-BUS (read)

IV3-BUS (read)

IV4-BUS (read)

LCD_VSYNC

LCD_HSYNC

LCD_DE
LCD_DATA15 to
LCD_DATA0

LCD_M_DISP

LCD_CLK

Input timing

control block

Capturing,

video scaling processing,

contrast adjustment,

brightness adjustment,

frame skipping

Video receiving block

Conversion

from YC to RGB

Conversion from 

RGB565 to 888

Write control

Write control

Read control

Read control

I-BUS

write control

I-BUS

write control

Conversion from 

RGB565 to 888

Write control

Read control

I-BUS

write control

Register

control

Sync signals

Peripheral bus

Video data
(RGB565 format)

Video supplying
block

Register control

Register control

Video data

read

α blending,

chroma-keying

Video

Video +

graphic

image 1

Video +
graphic images 
1 and 2

Output timing

control block

Sync signals

for video

Sync signals
for graphics

Video data
RGB565

Graphics 2
data

Graphics 1
data

Graphics block 1

Graphics block 2

Panel control

block

Synchronization

with Vsync from

video receiving

block

Register

control

Data enable

signal

generation

Conversion

from RGB888

to 565

Sync signal
generation

1. For graphics
2. For video
3. For output to panel

2-por

t RAM

256 w

ords x 32 bits x 2

2-por

t RAM

256 w

ords x 32 bits x 2

2-por

t RAM

384 w

ords x 32 bits x 2

2-por

t RAM

384 w

ords x 32 bits x 2