Renesas R5S72622 Manual Do Utilizador

 
Section 27   Video Display Controller 3 

Page 1576 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

0 OVER_FLOW 

0 

R/W*

3

 

Indicates the overflow status of the buffer used to 
write video data to the memory.*

1

*

2

 

0: No overflow has occurred. 

1: An overflow has occurred 

Notes:  1.  The status bits (bits 12, 8, 4, and 0) always operate, regardless of the settings of 

operation-enabling bits. After it has been set to 1, a status bit retains this value until it is 
cleared to 0. 

 

2.  The overflow flag is set to 1 in the cases shown below. 

 

 

(a) (The number of operations of writing to the buffer in the video display controller 3) 

  

 

 

 

(the number of operations of reading from the buffer) 

 amount of data for two lines 

 

 

(b) (The number of operations of writing to the buffer in the video display controller 3) 

  

 

 

 

(the number of operations of reading from the buffer) 

 

 

Case (a) arises when there is a shortage of IV1-BUS bandwidth. 

 

 

On the other hand, case (b) arises when less than the normal amount of data is written 
for one line, due to a malfunction of external input. 

 

3.  Only 0 can be written.