Renesas R5S72622 Manual Do Utilizador

 

Section 37   Electrical Characteristics 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1983 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

 = 72 MHz*

1

IOIS16 hold time 

T

IO16H

 1/2t

cyc

 + 3.5

 ns 

Figure

 

37.39 

RAS delay time 1 

t

RASD1

 

2*

4

 10.5 ns 

Figures

 

37.17 to 

37.33 

RAS delay time 2 

t

RASD2

 1/2t

cyc

 1/2t

cyc

 + 10.5 ns 

Figures

 

37.34, 37.35 

CAS delay time 1 

t

CASD1

 

2*

4

 10.5 ns 

Figures

 

37.17 to 

37.33 

CAS delay time 2 

t

CASD2

 1/2t

cyc

 1/2t

cyc

 + 10.5 ns 

Figures

 

37.34, 37.35 

DQM delay time 1 

t

DQMD1

 

2*

4

 10.5 ns 

Figures

 

37.17 to 

37.30 

DQM delay time 2 

t

DQMD2

 1/2t

cyc

 1/2t

cyc

 + 10.5 ns 

Figures

 

37.34, 37.35 

CKE delay time 1 

t

CKED1

 

2*

4

 10.5 ns 

Figure

 

37.32 

CKE delay time 2 

t

CKED2

 1/2t

cyc

 1/2t

cyc

 + 10.5 ns 

Figure

 

37.35 

AH delay time 

t

AHD

 1/2t

cyc

 1/2t

cyc

 + 10.5 ns 

Figure

 

37.13 

Multiplexed address delay 
time 

t

MAD

 

 10.5 ns 

Figure

 

37.13 

Multiplexed address hold time  t

MAH

 1 

 ns 

Figure

 

37.13 

Address setup time for 

AH 

t

AVVH

 1/2t

cyc

 – 2 

 ns 

Figure

 

37.13 

DACK, TEND delay time 

t

DACD

 

Refer to section 37.4.4, 
Direct Memory Access 
Controller Timing 

ns Figures

 

37.9 to 

37.30, 37.34, 37.36 
to 37.39 

ICIORD delay time 

t

ICRSD

 

 1/2t

cyc

 + 10.5 ns 

Figures

 

37.38, 37.39 

ICIOWR delay time 

t

ICWSD

 

 1/2t

cyc

 + 10.5 ns 

Figures

 

37.38, 37.39 

Notes:  1.  The maximum value (fmax) of B

 (external bus clock) depends on the number of wait 

cycles and the system configuration of your board. 

 2. 

1/2 

t

cyc

 indicated in minimum and maximum values for the item of delay, setup, and hold 

times represents a half cycle from the rising edge with a clock. That is, 1/2 t

cyc

 describes 

a reference of the falling edge with a clock. 

 

3.  Values when SDRAM is used. Be sure to make necessary settings in ACSWR. (For 

details, refer to the descriptions from section 9.4.8, AC Characteristics Switching 
Register (ACSWR), to section 9.4.10, Sequence to Write to ACSWR.) 

 

4.  Be sure to make necessary settings in ACSWR. (For details, refer to the descriptions 

from section 9.4.8, AC Characteristics Switching Register (ACSWR), to section 9.4.10, 
Sequence to Write to ACSWR.)