Renesas R5S72622 Manual Do Utilizador

R01UH0134EJ0400  Rev. 4.00  

 

Page 2067 of 2108 

Sep 24, 2014 

 

 

9.4.3   CSn Space Wait 
Control Register (CSnWCR) 
(n = 0 to 6) 

(3)  SDRAM 
  CS3WCR 

272 

Table amended 

4, 3 

TRWL[1:0]* 00 

R/W 

...
• Cycle number from the issuance of the WRITA 

command by this LSI until the completion of auto-

precharge in the SDRAM. 

Equivalent to the cycle number from the issuance 

of the WRITA command until the issuance of the 

ACTV command. Confirm that how many cycles 

are required between the WRITA command 

receive in the SDRAM and the auto-precharge 

activation, referring to each SDRAM data sheet. 

And set the cycle number so as not to exceed the 

cycle number specified by this bit. 

• Cycle number from the issuance of the WRIT 

command until the issuance of the PRE 

command. This is the case when accessing 

another low address in the same bank in bank 

active mode. 

9.5.5   MPX-I/O Interface 

301 

Description added 

The data cycle is the same as that in a normal space 
access. 

The delay cycles specified by SW[1:0] are inserted 
between the Ta3 and T1 cycles. The delay cycles specified 
by HW[1:0] are added after the T2 cycle. 

Figure 9.11 (1)   Access 
Timing for MPX Space 
(Address Cycle No Wait, 
Data Cycle No Wait) 

302 

Figure title amended 

Figure 9.11 (2)   Access 
Timing for MPX Space 
(Address Cycle No Wait, 
Assert Extension Cycle 1.5, 
Data Cycle No Wait, Negate 
Extension Cycle 1.5) 

303 Figure 

added