Renesas R5S72622 Manual Do Utilizador
R01UH0134EJ0400 Rev. 4.00
Page 2107 of 2108
Sep 24, 2014
UMSR1 ............................................. 1038
USBACSWR1 .................................. 1471
USBADDR ....................................... 1410
USBINDX ........................................ 1413
USBLENG ........................................ 1414
USBREQ .......................................... 1411
USBVAL .......................................... 1412
WRCSR .............................................. 667
WTCNT .............................................. 663
WTCSR .............................................. 664
XTALCTR ........................................ 1805
USBACSWR1 .................................. 1471
USBADDR ....................................... 1410
USBINDX ........................................ 1413
USBLENG ........................................ 1414
USBREQ .......................................... 1411
USBVAL .......................................... 1412
WRCSR .............................................. 667
WTCNT .............................................. 663
WTCSR .............................................. 664
XTALCTR ........................................ 1805
Relationship between access size
and number of bursts .............................. 314
Relationship between refresh requests
and bus cycles ......................................... 333
Renesas serial peripheral interface ......... 775
Renesas serial peripheral interface
timing .................................................... 2019
Renesas SPDIF interface ...................... 1151
Reset sequence ...................................... 1054
Reset state ................................................. 93
Reset-synchronized PWM mode ............ 536
Restoration from bank ............................ 203
Restoration from stack ............................ 204
Restriction on direct memory access
controller usage ....................................... 772
RISC-type instruction set .......................... 56
Roles of mailboxes ................................. 990
Rounding ................................................ 105
and number of bursts .............................. 314
Relationship between refresh requests
and bus cycles ......................................... 333
Renesas serial peripheral interface ......... 775
Renesas serial peripheral interface
timing .................................................... 2019
Renesas SPDIF interface ...................... 1151
Reset sequence ...................................... 1054
Reset state ................................................. 93
Reset-synchronized PWM mode ............ 536
Restoration from bank ............................ 203
Restoration from stack ............................ 204
Restriction on direct memory access
controller usage ....................................... 772
RISC-type instruction set .......................... 56
Roles of mailboxes ................................. 990
Rounding ................................................ 105
S
Sampling rate converter ........................ 1637
Saving to bank ........................................ 202
Saving to stack ........................................ 204
Scan mode ............................................ 1273
SD host interface .................................. 1667
SD host interface timing ....................... 2040
SDRAM interface ................................... 306
Searching cache ...................................... 218
Saving to bank ........................................ 202
Saving to stack ........................................ 204
Scan mode ............................................ 1273
SD host interface .................................. 1667
SD host interface timing ....................... 2040
SDRAM interface ................................... 306
Searching cache ...................................... 218
Sector access mode ............................... 1327
Self-refreshing ........................................ 331
Sending a break signal ............................ 772
Serial bit clock control ............................ 936
Serial communication interface
with FIFO ................................................ 707
Serial communication interface
with FIFO timing .................................. 2018
Serial I/O with FIFO ............................... 939
Serial I/O with FIFO timing .................. 2027
Serial sound interface .............................. 893
Serial sound interface timing ................ 2025
Setting analog input voltage .................. 1282
Setting I/O ports for controller area
network ................................................. 1080
Shift instructions ....................................... 83
Sign extension of word data ...................... 56
Single address mode ............................... 420
Single mode .......................................... 1268
Single read .............................................. 318
Single write ............................................. 321
Slave mode operation .............................. 841
Slave receive operation ........................... 876
Slave transmit operation.......................... 873
Sleep mode .................................. 1055, 1806
Slot illegal instructions ........................... 148
Software standby mode ......................... 1807
SRAM interface with byte selection ....... 344
Stack after interrupt exception
handling .................................................. 194
Stack status after exception
handling ends .......................................... 151
Standby control circuit ............................ 117
Status register (SR) ................................... 50
Stopping and resuming CD-DSP
operation ............................................... 1257
Supported DMA transfers ....................... 417
Syndrome calculation ............................ 1248
System configuration example ................ 810
System control instructions ....................... 85
Self-refreshing ........................................ 331
Sending a break signal ............................ 772
Serial bit clock control ............................ 936
Serial communication interface
with FIFO ................................................ 707
Serial communication interface
with FIFO timing .................................. 2018
Serial I/O with FIFO ............................... 939
Serial I/O with FIFO timing .................. 2027
Serial sound interface .............................. 893
Serial sound interface timing ................ 2025
Setting analog input voltage .................. 1282
Setting I/O ports for controller area
network ................................................. 1080
Shift instructions ....................................... 83
Sign extension of word data ...................... 56
Single address mode ............................... 420
Single mode .......................................... 1268
Single read .............................................. 318
Single write ............................................. 321
Slave mode operation .............................. 841
Slave receive operation ........................... 876
Slave transmit operation.......................... 873
Sleep mode .................................. 1055, 1806
Slot illegal instructions ........................... 148
Software standby mode ......................... 1807
SRAM interface with byte selection ....... 344
Stack after interrupt exception
handling .................................................. 194
Stack status after exception
handling ends .......................................... 151
Standby control circuit ............................ 117
Status register (SR) ................................... 50
Stopping and resuming CD-DSP
operation ............................................... 1257
Supported DMA transfers ....................... 417
Syndrome calculation ............................ 1248
System configuration example ................ 810
System control instructions ....................... 85