Renesas R5S72622 Manual Do Utilizador
Section 9 Bus State Controller
Page 250 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
1, 0
HW[1:0]
00
R/W
Delay Cycles from RD,
WEn Negation to Address,
CS0 Negation
Specify the number of delay cycles from RD and
Specify the number of delay cycles from RD and
WEn
negation to address and
CS0 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Note: * To connect the burst ROM to the CS0 space and switch to burst ROM interface after
activation, set the TYPE[2:0] bits in CS0BCR after setting the burst number by the bits
20 and 21 and the burst wait cycle number by the bits 16 and 17. Do not write 1 to the
reserved bits other than above bits.
20 and 21 and the burst wait cycle number by the bits 16 and 17. Do not write 1 to the
reserved bits other than above bits.
CS1WCR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R/W
R
R/W
R/W
R/W
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
-
-
-
-
-
-
-
-
-
-
-
BAS
-
WW[2:0]
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 21
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.