Renesas R5S72622 Manual Do Utilizador

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Section 9   Bus State Controller 
 
Page 302 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
T1
CKIO
A25 to A0
CS5
RD/
WR
RD
D15/D7 to D0
WEn
D15/D7 to D0
BS
Read
Write
T2
DACKn*
Ta1
Ta2
Ta3
AH
Address
Address
Data
Data
Note: * The waveform for DACKn is when active low is specified.
 
Figure 9.11 (1)   Access Timing for MPX Space 
(Address Cycle No Wait, Data Cycle No Wait)