Renesas R5S72622 Manual Do Utilizador

 

 

 

 

 

Section 10   Direct Memory Access Controller 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 409 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Figure 10.2 is a flowchart of this procedure. 

No

No

Yes

Yes

No

No

Yes

Yes

No

No

No

*

2

Yes

Yes

Yes

In

 

DREQ  

detection by level in external  

request mode, or in on-chip peripheral 

 module request mode,  

TEMASK = 1?

Start

Initial settings       

(SAR, DAR, DMATCR, CHCR, DMAOR, DMARS)

DE, DME = 1 and

NMIF, AE, TE = 0?

Transfer request

occurs?*

1

Transfer (one transfer unit);

DMATCR – 1 

→ DMATCR, 

SAR and DAR updated

DMATCR = 0?

TE = 1

DEI interrupt request

(when IE = 1)

When reload function is enabled,

RSAR 

→ SAR, RDAR → DAR,

and RDMATCR 

→ DMATCR

For a request from an

on-chip peripheral module,

the transfer acknowledge signal

is sent to the module.

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

Transfer end

Bus mode,

transfer request mode,

 DREQ detection system

DMATCR = 1/2 ?

HE = 1

HEI interrupt request

(when HE = 1)

When the TC bit in CHCR is 0, or  

for a request from an on-chip peripheral

module, the transfer acknowledge

signal is sent to the module. 

NMIF = 1

or AE = 1 or DE = 0

or DME = 0?

*

3

Normal end

Transfer terminated

Notes:  1.  In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the 

DE and DME bits are set to 1.

 

2.  DREQ level detection in burst mode (external request) or cycle steal mode.

 3. 

DREQ

 edge detection in burst mode (external request), or auto request mode in burst mode.