Renesas R5S72622 Manual Do Utilizador
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 579 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Basic Operation Example of A/D Converter Start Request Delaying Function
Figure 11.74 shows a basic example of A/D converter request signal (TRG4AN) operation
when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter
start request signal is output during TCNT_4 down-counting.
when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter
start request signal is output during TCNT_4 down-counting.
TADCORA_4
TADCOBRA_4
TCNT_4
Transfer from cycle buffer
register to cycle register
register to cycle register
Transfer from cycle buffer
register to cycle register
register to cycle register
Transfer from cycle buffer
register to cycle register
register to cycle register
A/D converter start request
(TRG4AN)
(Complementary PWM mode)
Figure 11.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation
Buffer Transfer
The data in the timer A/D converter start request cycle set registers (TADCORA_4 and
TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer
registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits
in the timer A/D converter start request control register (TADCR_4).
TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer
registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits
in the timer A/D converter start request control register (TADCR_4).
A/D Converter Start Request Delaying Function Linked with Interrupt Skipping
A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR).
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR).
Figure 11.75 shows an example of A/D converter start request signal (TRG4AN) operation
when TRG4AN output is enabled during TCNT_4 up counting and down counting and A/D
converter start requests are linked with interrupt skipping.
when TRG4AN output is enabled during TCNT_4 up counting and down counting and A/D
converter start requests are linked with interrupt skipping.
Figure 11.76 shows another example of A/D converter start request signal (TRG4AN)
operation when TRG4AN output is enabled during TCNT_4 up counting and A/D converter
start requests are linked with interrupt skipping.
operation when TRG4AN output is enabled during TCNT_4 up counting and A/D converter
start requests are linked with interrupt skipping.