Renesas R5S72622 Manual Do Utilizador
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 597 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the direct memory
access controller is activated, the flag is cleared automatically. Figure 11.96 shows the timing for
status flag clearing by the CPU, and Figure 11.97 shows the timing for status flag clearing by the
direct memory access controller.
access controller is activated, the flag is cleared automatically. Figure 11.96 shows the timing for
status flag clearing by the CPU, and Figure 11.97 shows the timing for status flag clearing by the
direct memory access controller.
Status flag
Write signal
Address
TSR address
Interrupt
request signal
request signal
TSR write cycle
T1
T2
P
φ
Figure 11.96 Timing for Status Flag Clearing by CPU
Interrupt
request signal
request signal
Flag clear
signal
signal
Status flag
Address
Source address
Direct memory
access controller
read cycle
Destination
address
Direct memory
access controller
write cycle
P
φ, Bφ
Figure 11.97 Timing for Status Flag Clearing by Direct Memory Access Controller
Activation