Renesas R5S72622 Manual Do Utilizador

 

 

Section 16   Renesas Serial Peripheral Interface 

 

 

Page 782 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

5 

SPTIE 

0 

R/W 

Transmit Interrupt Enable 

Enables or disables generation of transmit interrupt 
requests (SPTI) when the number of transmit data 
units in the transmit buffer (SPTX) is equal to or less 
than the specified transmit buffer data triggering 
number and the SPTEF flag in SPSR is set to 1. 

0: Disables the generation of transmit interrupt 

requests. 

1: Enables the generation of transmit interrupt 

requests. 

4 

SPEIE 

0 

R/W 

Error Interrupt Enable 

Enables or disables the generation of error interrupt 
requests when this module detects a mode fault 
error and sets the MODF bit in the status register 
(SPSR) to 1, or when this module detects an overrun 
error and sets the OVRF bit in SPSR to 1 (see 
section 16.4.6, Error Detection). 

0: Disables the generation of error interrupt 

requests. 

1: Enables the generation of error interrupt requests. 

Note: This bit is valid only in SPI slave mode. 

3 

MSTR 

0 

R/W 

Master/Slave Mode Select  

Selects master/slave mode. According to MSTR bit 
settings, this module determines the direction of pins 
RSPCK, MOSI, MISO, and SSL pins. 

0: Slave mode 

1: Master mode 

2 

MODFEN 

0 

R/W 

Mode Fault Error Detection Enable 

Enables or disables the detection of mode fault 
errors (see section 16.4.6, Error Detection).  

0: Disables the detection of mode fault errors 

1: Enables the detection of mode fault errors 

Note: This bit is valid only in SPI slave mode. When 

master mode is specified with the MSTR bit, 
this bit should always be cleared to 0. 

1, 0 

 All 

0 

R 

Reserved 

The write value should always be 0. Otherwise, 
operation cannot be guaranteed.