Renesas R5S72622 Manual Do Utilizador

 
Section 17   I

2

C Bus Interface 3 

Page 850 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

Figure 17.1 shows a block diagram. 

SCL

ICCR1

ICCR2

ICMR

ICSR

ICIER

ICDRR

ICDRS

ICDRT

SAR

SDA

NF2CYC

Transfer clock

generation

circuit

Address

comparator

Interrupt

generator

Interrupt 
request

Bus state

decision circuit

Arbitration

decision circuit

Noise canceler

Noise filter

Output
control

Output
control

Transmission/

reception

control circuit

I

2

C bus control register 1

I

2

C bus control register 2

I

2

C bus mode register 

I

2

C bus status register 

I

2

C bus interrupt enable register

I

2

C bus transmit data register 

I

2

C bus receive data register

I

2

C bus shift register

Slave address register
NF2CYC register

 

[Legend]

ICCR1:
ICCR2:
ICMR:
ICSR:
ICIER:
ICDRT:
ICDRR:
ICDRS:
SAR:
NF2CYC:

Peripheral bus