Renesas R5S72621 Manual Do Utilizador
Section 2 CPU
Page 64 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Addressing
Mode
Mode
Instruction
Format
Format
Effective Address Calculation
Equation
Immediate
#imm:20
The 20-bit immediate data (imm) for the MOVI20
instruction is sign-extended.
Sign-
extended
imm (20 bits)
31
19
0
The 20-bit immediate data (imm) for the MOVI20S
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits are
padded with zero.
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits are
padded with zero.
Sign-extended
imm (20 bits) 00000000
31 27
8
0
#imm:8
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
OR, and XOR instructions is zero-extended.
#imm:8
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions is sign-extended.
and CMP/EQ instructions is sign-extended.
#imm:8
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
instruction is zero-extended and then quadrupled.
#imm:3
The 3-bit immediate data (imm) for the BAND, BOR,
BXOR, BST, BLD, BSET, and BCLR instructions
indicates the target bit location.
BXOR, BST, BLD, BSET, and BCLR instructions
indicates the target bit location.