Renesas R5S72621 Manual Do Utilizador
Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00
Page 1021 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit 7 - Overload Frame (IRR7): Flag indicating that this module has detected a condition that
should initiate the transmission of an overload frame. Note that in the condition of transmission
being prevented, such as listen only mode, an Overload Frame will NOT be transmitted, but IRR7
will still be set. IRR7 remains asserted until reset by writing a '1' to this bit position - writing a '0'
has no effect.
should initiate the transmission of an overload frame. Note that in the condition of transmission
being prevented, such as listen only mode, an Overload Frame will NOT be transmitted, but IRR7
will still be set. IRR7 remains asserted until reset by writing a '1' to this bit position - writing a '0'
has no effect.
Bit 7: IRR7
Description
0 [Clearing
condition]
Writing 1 (Initial value)
1
[Setting conditions] Overload condition detected
Bit 6 - Bus Off Interrupt Flag (IRR6): This bit is set when this module enters the Bus-off state
or when this module leaves Bus-off and returns to Error-Active. The cause therefore is the existing
condition TEC
or when this module leaves Bus-off and returns to Error-Active. The cause therefore is the existing
condition TEC
256 at the node or the end of the Bus-off recovery sequence (128X11
consecutive recessive bits) or the transition from Bus Off to Halt (automatic or manual). This bit
remains set even if this module node leaves the bus-off condition, and needs to be explicitly
cleared by S/W. The S/W is expected to read the GSR0 to judge whether this module is in the bus-
off or error active status. It is cleared by writing a '1' to this bit position even if the node is still
bus-off. Writing a '0' has no effect.
remains set even if this module node leaves the bus-off condition, and needs to be explicitly
cleared by S/W. The S/W is expected to read the GSR0 to judge whether this module is in the bus-
off or error active status. It is cleared by writing a '1' to this bit position even if the node is still
bus-off. Writing a '0' has no effect.
Bit 6: IRR6
Description
0 [Clearing
condition]
Writing 1 (Initial value)
1
Enter Bus off state caused by transmit error or Error Active state returning
from Bus-off
from Bus-off
[Setting condition]
When TEC becomes
256 or End of Bus-off after 128X11 consecutive
recessive bits or transition from Bus Off to Halt
Bit 5 - Error Passive Interrupt Flag (IRR5): Interrupt flag indicating the error passive state
caused by the transmit or receive error counter or by Error Passive forced by test mode. This bit is
reset by writing a '1' to this bit position, writing a '0' has no effect. If this bit is cleared the node
may still be error passive. Please note that the SW needs to check GSR0 and GSR5 to judge
whether this module is in Error Passive or Bus Off status.
caused by the transmit or receive error counter or by Error Passive forced by test mode. This bit is
reset by writing a '1' to this bit position, writing a '0' has no effect. If this bit is cleared the node
may still be error passive. Please note that the SW needs to check GSR0 and GSR5 to judge
whether this module is in Error Passive or Bus Off status.
Bit 5: IRR5
Description
0 [Clearing
condition]
Writing 1 (Initial value)
1
Error passive state caused by transmit/receive error
[Setting condition]
When TEC
128 or REC 128 or Error Passive test mode is used