Renesas R5S72621 Manual Do Utilizador
Section 22 Renesas SPDIF Interface
R01UH0134EJ0400 Rev. 4.00
Page 1163 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
8
CSE
0
R/WC0 Channel Status Error*
Sets when the channel status information is written
before the 32nd frame of the current block. This bit is
cleared by writing 0. If bits TEIE and CSEI in the control
register are set this causes an interrupt.
before the 32nd frame of the current block. This bit is
cleared by writing 0. If bits TEIE and CSEI in the control
register are set this causes an interrupt.
0: Channel status correct
1: Channel status error
7
ABO
0
R/WC0 Audio Buffer Overrun*
Indicates that the receiver audio buffer is full in both the
first and second stages and that data has been
overwritten. This bit is cleared by writing 0. If bits REIE
and ABOI in the control register are set then this causes
an interrupt.
first and second stages and that data has been
overwritten. This bit is cleared by writing 0. If bits REIE
and ABOI in the control register are set then this causes
an interrupt.
0: Receiver audio buffer has not overrun
1: Receiver audio buffer has overrun
6
ABU
0
R/WC0 Audio Buffer Underrun*
Indicates that the transmitter audio buffer is empty in both
the first and second stages and that the last data
transmission has been repeated. This bit is cleared by
writing 0. If bits TEIE and ABUI in the control register are
set then this causes an interrupt.
the first and second stages and that the last data
transmission has been repeated. This bit is cleared by
writing 0. If bits TEIE and ABUI in the control register are
set then this causes an interrupt.
0: Transmitter audio buffer has not underrun
1: Transmitter audio buffer has underrun
5
RUIR
0
R
Receiver User Information Register Status
Indicates the status of the receiver user information
register. This bit is cleared by reading from the receiver
user register. If bit RUII in the control register is set then
this causes an interrupt.
register. This bit is cleared by reading from the receiver
user register. If bit RUII in the control register is set then
this causes an interrupt.
0: Receiver user information register is empty
1: Receiver user information register is full
4
TUIR
0
R
Transmitter User Information Register Status
Indicates the status of the transmitter user information
register. This bit is cleared by writing to the transmitter
user register. If bit TUII in the control register is set then
this causes an interrupt.
register. This bit is cleared by writing to the transmitter
user register. If bit TUII in the control register is set then
this causes an interrupt.
0: Transmitter user information register is full
1: Transmitter user information register is empty