Renesas R5S72621 Manual Do Utilizador
Section 22 Renesas SPDIF Interface
Page 1184 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Figure 22.6 shows a data transfer with a DMA transfer for the transmitter.
Start
Idle
Enter idle state?
No
Yes
Wait for transmitter
DMA request
Load left or right audio
channel data
Figure 22.6 Transmitter Data Transfer Flow Diagram—DMA Request Driven
Channel status information is required to be updated when the information has changed. Because
the updating needs to be done before the transmission of the next block, the channel status to be
updated should be written after 30 frames have been sent; this is indicated either by an interrupt or
by polling the status bit. If channel status is written before 30 frames have been sent (while current
information is being sent) then an interrupt indicates that the channel status error bit (CSE) in the
status register has been set.
the updating needs to be done before the transmission of the next block, the channel status to be
updated should be written after 30 frames have been sent; this is indicated either by an interrupt or
by polling the status bit. If channel status is written before 30 frames have been sent (while current
information is being sent) then an interrupt indicates that the channel status error bit (CSE) in the
status register has been set.
Note:
30 frames contains all the valid information in a single channel status block.