Renesas R5S72621 Manual Do Utilizador
Section 25 NAND Flash Memory Controller
Page 1334 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(2) 4-Symbol ECC Operation
Figure 25.16 shows a flowchart of the operation when the 4-symbol ECC circuit is used. Setting
the 4ECCEN bit in FLCMNCR enables the 4-symbol ECC circuit and ECC is generated and
output for each sector. If the 4ECCCORRECT bit in FLCMNCR is also set to 1, information
necessary for correction pattern generation is accumulated in the 4-symbol ECC circuit.
the 4ECCEN bit in FLCMNCR enables the 4-symbol ECC circuit and ECC is generated and
output for each sector. If the 4ECCCORRECT bit in FLCMNCR is also set to 1, information
necessary for correction pattern generation is accumulated in the 4-symbol ECC circuit.
In the case when the NAND flash memory controller is reading data from flash memory by
continuous sector access, the reading operation stops when an error-containing sector has been
read regardless of the number of remaining sectors. After reading of the error-containing sector
has ended, generation of error correction pattern is started by setting the FL4ECCCR register. If
the sector contains five or more errors, that sector is regarded as uncorrectable. Note that a sector
may be uncorrectable for some error patterns even if it contains four or less errors. In such a case,
invalid data are placed in the FL4ECCRES1 to FL4ECCRES4 registers.
continuous sector access, the reading operation stops when an error-containing sector has been
read regardless of the number of remaining sectors. After reading of the error-containing sector
has ended, generation of error correction pattern is started by setting the FL4ECCCR register. If
the sector contains five or more errors, that sector is regarded as uncorrectable. Note that a sector
may be uncorrectable for some error patterns even if it contains four or less errors. In such a case,
invalid data are placed in the FL4ECCRES1 to FL4ECCRES4 registers.