Renesas R5S72621 Manual Do Utilizador
Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00
Page 1569 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 27.10 Register Configuration in Display Control Block
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
SG mode register
SGMODE
R/W
H'0000 0000
H'FFFF 3800 32, 16, 8
Interrupt output control register SGINTCNT
R/W
H'0000 0000
H'FFFF 3804 32, 16, 8
Sync signal control register
SYNCNT
R/W
H'0000 0000
H'FFFF 3808 32, 16, 8
Panel clock select register
PANEL_CLKSEL
R/W
H'0000 0001
H'FFFF 380C 32, 16, 8
Sync signal size register
SYN_SIZE
R/W
H'020D 035A
H'FFFF 3900 32, 16, 8
Timing control register for
vertical sync signal for output to
panel
vertical sync signal for output to
panel
PANEL_VSYNC_TIM
R/W
H'0000 0001
H'FFFF 3904 32, 16, 8
Timing control register for
horizontal sync signal for output
to panel
horizontal sync signal for output
to panel
PANEL_HSYNC_TIM
R/W
H'0000 000A
H'FFFF 3908 32, 16, 8
Timing control register 2 for
vertical sync signal for video
vertical sync signal for video
VIDEO_VSYNC_TIM2 R/W
H'0000 0000
H'FFFF 390C 32, 16, 8
Timing control register for
vertical sync signal for graphics
image
vertical sync signal for graphics
image
GRA_VSYNC_TIM
R/W
H'0000 0000
H'FFFF 3910 32, 16, 8
AC modulation signal toggle
line count
line count
AC_LINE_NUM
R/W
H'0000 000C
H'FFFF 3914 32, 16, 8
DE area size register
DE_SIZE
R/W
H'0000 0000
H'FFFF 3920 32, 16, 8
DE area start position register
DE_START
R/W
H'0000 0000
H'FFFF 3924 32, 16, 8