Renesas R5S72621 Manual Do Utilizador

 

Section 27   Video Display Controller 3 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1575 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

16 INT_OF_EN 

0 R/W 

Enables 

output of overflow interrupts. 

0: Disabled 

1: Enabled 

15 to 13 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

12 V_PERIOD 

0 R/W*

3

 

Indicates the VSYNC cycle fluctuation status in the 
input video. 

0:  The VSYNC cycles in the input video are 

constant. 

1:  The VSYNC cycles in the input video are not 

constant. 

11 to 9 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

8 F_END 0 

R/W*

3

 

Indicates the status of writing one field of video 
data to the memory.*

1

 

0: Writing is in progress. 

1: Writing has been completed. 

7 to 5 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

4 UNDER_FLOW 

0 

R/W*

3

 

Indicates the underflow status of the buffer used to 
read video data from the memory.*

1

 

0: No underflow has occurred. 

1: An underflow has occurred. 

3 to 1 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0.