Renesas R5S72621 Manual Do Utilizador
Section 5 Clock Pulse Generator
Page 124 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
5, 4
IFC[1:0]
01/10*
R/W
CPU Clock Frequency Division Ratio
This bit specifies the frequency division ratio of the
CPU clock with respect to the output frequency of PLL
circuit.
CPU clock with respect to the output frequency of PLL
circuit.
00: 1 time
01: 1/2 times
10: 1/3 times
11: Reserved (setting prohibited)
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
2 to 0
PFC[2:0]
100/011* R/W
Peripheral Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit.
peripheral clock with respect to the output frequency
of PLL circuit.
000: Reserved (setting prohibited)
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: 1/4 times
100: 1/6 times
101: 1/8 times
110: 1/12 times
111: Reserved (setting prohibited)
Note: * The initial value changes depending on the clock mode.