Renesas R5S72621 Manual Do Utilizador

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Section 28   Sampling Rate Converter 
R01UH0134EJ0400  Rev. 4.00  
 
Page 1657 of 2108 
Sep 24, 2014 
 
 
 
SH7262 Group, SH7264 Group 
Bit Bit 
Name 
Initial 
Value R/W Description 
0 OINT
0 R/(W)*
1
Output Data FIFO Full Interrupt Request Flag 
Indicates that the number of data units in the output 
FIFO has become equal to or greater than the 
triggering number specified by the OFTRG[1:0] bits in 
the output data control register (SRCODCTRL). 
[Clearing conditions] 
  When 0 has been written to the OINT bit after 
reading OINT = 1. 
  When the number of data units in the FIFO has 
become less than the specified triggering number 
due to DMA transfer to the output FIFO. 
  When 1 has been written to the CL bit in 
SRCCTRL.*
2
 
  When 1 has been written to the SRCEN bit in 
SRCCTRL while SRCEN is 0.*
2
 
[Setting condition] 
  When the number of data units in the output FIFO 
has become equal to or greater than the specified 
triggering number. 
Notes:  1.  Only 0 can be written after having read as 1. 
 
2.  The setting is valid only in channel 0. In channel 1, the setting is invalid.