Renesas R5S72621 Manual Do Utilizador
Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00
Page 133 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Exception
Source
Timing of Source Detection and Start of Handling
Instructions
Trap instruction
Starts from the execution of a TRAPA instruction.
General illegal
instructions
instructions
Starts from the decoding of undefined code anytime except
immediately after a delayed branch instruction (delay slot)
(including FPU instructions and FPU-related CPU instructions
in FPU module standby state).
immediately after a delayed branch instruction (delay slot)
(including FPU instructions and FPU-related CPU instructions
in FPU module standby state).
Slot illegal
instructions
instructions
Starts from the decoding of undefined code placed directly after
a delayed branch instruction (delay slot) (including FPU
instructions and FPU-related CPU instructions in FPU module
standby state), of instructions that rewrite the PC, of 32-bit
instructions, of the RESBANK instruction, of the DIVS
instruction, or of the DIVU instruction.
a delayed branch instruction (delay slot) (including FPU
instructions and FPU-related CPU instructions in FPU module
standby state), of instructions that rewrite the PC, of 32-bit
instructions, of the RESBANK instruction, of the DIVS
instruction, or of the DIVU instruction.
Integer division
exceptions
exceptions
Starts when detecting division-by-zero exception or overflow
exception caused by division of the negative maximum value
(H'80000000) by
exception caused by division of the negative maximum value
(H'80000000) by
1.
Instructions
FPU exceptions
Starts when detecting invalid floating point operation exception
defined by IEEE standard 754, division-by-zero exception,
overflow, underflow, or inexact exception.
defined by IEEE standard 754, division-by-zero exception,
overflow, underflow, or inexact exception.
Also starts when qNaN or
is input to the source for a floating
point operation instruction when the QIS bit in FPSCR is set.
When exception handling starts, the CPU operates as follows:
(1) Exception Handling Triggered by Reset
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004
addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets).
See section 6.1.3, Exception Handling Vector Table, for more information. The vector base
register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the
status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The
BN bit in IBNR of the interrupt controller is also initialized to 0. The floating point status/control
register (FPSCR) is initialized to H'00040001 by a power-on reset. The program begins running
from the PC address fetched from the exception handling vector table.
exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004
addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets).
See section 6.1.3, Exception Handling Vector Table, for more information. The vector base
register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the
status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The
BN bit in IBNR of the interrupt controller is also initialized to 0. The floating point status/control
register (FPSCR) is initialized to H'00040001 by a power-on reset. The program begins running
from the PC address fetched from the exception handling vector table.