Renesas R5S72621 Manual Do Utilizador
Section 33 Power-Down Modes
Page 1792 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
1
1
1
1
1
1
1
1
R
R
R/W
R/W
R/W
R/W
R/W
R/W
-
-
VRA
ME5
ME5
VRA
ME4
ME4
VRA
ME3
ME3
VRA
ME2
ME2
VRA
ME0
ME0
VRA
ME1
ME1
Bit Bit
Name
Initial
Value
Value
R/W Description
7, 6
All
1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
should always be 1.
5
VRAME5
1
R/W
RAM Enable 5 (corresponding area: page 5* in large-
capacity on-chip RAM)
capacity on-chip RAM)
0: Access to page 5 is disabled.
1: Access to page 5 is enabled.
Note: This bit is reserved in 640-Kbyte version and
read as 1. The write value should always be 0.
4
VRAME4
1
R/W
RAM Enable 4 (corresponding area: page 4* in large-
capacity on-chip RAM)
capacity on-chip RAM)
0: Access to page 4 is disabled.
1: Access to page 4 is enabled.
3
VRAME3
1
R/W
RAM Enable 3 (corresponding area: page 3* in large-
capacity on-chip RAM)
capacity on-chip RAM)
0: Access to page 3 is disabled.
1: Access to page 3 is enabled.
2
VRAME2
1
R/W
RAM Enable 2 (corresponding area: page 2* in large-
capacity on-chip RAM
capacity on-chip RAM
0: Access to page 2 is disabled.
1: Access to page 2 is enabled.
1
VRAME1
1
R/W
RAM Enable 1 (corresponding area: page 1* in large-
capacity on-chip RAM
capacity on-chip RAM
0: Access to page 1 is disabled.
1: Access to page 1 is enabled.
0
VRAME0
1
R/W
RAM Enable 0 (corresponding area: page 0* in large-
capacity on-chip RAM)
capacity on-chip RAM)
0: Access to page 0 is disabled.
1: Access to page 0 is enabled.
Note: * For addresses in each page, see section 31, On-Chip RAM.