Renesas R5S72621 Manual Do Utilizador
Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00
Page 307 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Figures 9.14 shows an example of the connection of the SDRAM with the LSI.
A14
A1
CKE
CKIO
CSn
RAS
CAS
CAS
RD/
WR
D15
D0
DQMU
DQML
64M SDRAM
(1M
× 16-bit × 4-bank)
. . .
A13
A0
CKE
CLK
CS
CS
RAS
CAS
WE
I/O15
CAS
WE
I/O15
I/O0
DQMU
DQML
. . .
. . .
. . .
This LSI
Figure 9.14 Example of 16-Bit Data Width SDRAM Connection
(2) Address Multiplexing
An address multiplexing is specified so that SDRAM can be connected without external
multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR and bits A2ROW[1:0],
A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 9.9 to 9.11 show the relationship
between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and
A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other
than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not
multiplexed and the original values of address are always output at these pins.
multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR and bits A2ROW[1:0],
A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 9.9 to 9.11 show the relationship
between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and
A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other
than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not
multiplexed and the original values of address are always output at these pins.
When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word
address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of
SDRAM to the A2 pin of the LSI, and so on.
address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of
SDRAM to the A2 pin of the LSI, and so on.