Renesas R5S72621 Manual Do Utilizador
Section 9 Bus State Controller
Page 350 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(1) Basic Timing for Memory Card Interface
Figure 9.39 shows the basic timing of the PCMCIA IC memory card interface. When areas 5 and 6
are specified as the PCMCIA interface, the bus is accessed with the IC memory card interface
according to the SA[1:0] bit settings in CS5WCR and CS6WCR. If the external bus frequency
(CKIO) increases, the setup times and hold times for the address pins (A25 to A0), card enable
signals (
are specified as the PCMCIA interface, the bus is accessed with the IC memory card interface
according to the SA[1:0] bit settings in CS5WCR and CS6WCR. If the external bus frequency
(CKIO) increases, the setup times and hold times for the address pins (A25 to A0), card enable
signals (
CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) to the RD and WE signals
become insufficient. To prevent this error, this LSI enables the setup times and hold times for
areas 5 and 6 to be specified independently, using CS5WCR and CS6WCR. In the PCMCIA
interface, as in the normal space interface, a software wait or hardware wait using the
areas 5 and 6 to be specified independently, using CS5WCR and CS6WCR. In the PCMCIA
interface, as in the normal space interface, a software wait or hardware wait using the
WAIT pin
can be inserted. Figure 9.40 shows the PCMCIA memory bus wait timing.
Tpcm1w
CKIO
A25 to A0
CExx
RD/
WR
RD
D15 to D0
WE
D15 to D0
BS
Read
Write
Tpcm2
Tpcm1
Tpcm1w
Tpcm1w
Figure 9.39 Basic Access Timing for PCMCIA Memory Card Interface