Renesas R5S72621 Manual Do Utilizador

 

 

 

 

 

Section 10   Direct Memory Access Controller 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 387 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

26 

DAF 

0 

R/W 

Fixed Destination Address 16-Byte Transfer 

Enabled when the transfer size (set in TS[1:0]) is 16 
bytes and the destination address mode (set in 
DM[1:0]) is fixed address. 

0: 16 bytes of data are transferred to the address set in 

the DAR register. The write destination address is 
the address set in the DAR register + H'0, + H'4, + 
H'8, or + H'C. 

1: Four bytes of data are transferred four times to the 

address set in the DAR register. The write 
destination address is fixed at the address set in the 
DAR register. 

This function is exclusively for use with the CD-ROM 
decoder, USB 2.0 host/function module, and sampling 
rate converter. 

25 

SAF 

0 

R/W 

Fixed Source Address 16-Byte Transfer 

Enabled when the transfer size (set in TS[1:0]) is 16 
bytes and the source address mode (set in SM[1:0]) is 
fixed address. 

0: 16 bytes of data are transferred from the address 

specified in SAR. The read address is the address 
set in the SAR register + H'0, + H'4, + H'8, or + H'C.

1: Four bytes of data are transferred four times from 

the address specified in SAR. The read address is 
fixed at the address set in the SAR register. 

This function is exclusively for use with the CD-ROM 
decoder, USB 2.0 host/function module, and sampling 
rate converter. 

24 

 0 

R 

Reserved 

This bit is always read as 0. The write value should 
always be 0. 

23 DO 

0  R/W 

DMA 

Overrun 

Selects whether DREQ is detected by overrun 0 or by 
overrun 1. This bit is valid only in level detection by 
CHCR_0 and CHCR_1*

1

. This bit is reserved in 

CHCR_2 to CHCR_15*

2

; it is always read as 0 and the 

write value should always be 0. 

0: Detects DREQ by overrun 0 

1: Detects DREQ by overrun 1