Renesas R5S72621 Manual Do Utilizador
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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00
Page 393 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7
6
DL
DS
0
0
R/W
R/W
DREQ Level
DREQ Edge Select
These bits specify the sampling method of the DREQ
pin input and the sampling level.
pin input and the sampling level.
These bits are valid only in CHCR_0 and CHCR_1*
1
.
These bits are reserved in CHCR_2 to CHCR_15*
2
;
they are always read as 0 and the write value should
always be 0.
always be 0.
If the transfer request source is specified as an on-chip
peripheral module or if an auto-request is specified, the
specification by these bits is ignored.
peripheral module or if an auto-request is specified, the
specification by these bits is ignored.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5 TB
0 R/W
Transfer
Bus
Mode
Specifies the bus mode at DMA transfer. Note that the
burst mode must not be selected when TC = 0.
burst mode must not be selected when TC = 0.
0: Cycle steal mode
1: Burst mode
4, 3
TS[1:0]
00
R/W
Transfer Size
These bits specify the size of data to be transferred.
Select the size of data to be transferred when the
source or destination is an on-chip peripheral module
register of which transfer size is specified.
source or destination is an on-chip peripheral module
register of which transfer size is specified.
00: Byte unit
01: Word unit (two bytes)
10: Longword unit (four bytes)
11: 16-byte (four longword) unit