Renesas R5S72621 Manual Do Utilizador
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 479 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
0 ITB4VE
0*
R/W
TCIV_4 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4BN) with TCIV_4 interrupt skipping operation.
(TRG4BN) with TCIV_4 interrupt skipping operation.
0: Does not link with TCIV_4 interrupt skipping
1: Links with TCIV_4 interrupt skipping
Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits.
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR
and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with
interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the
timer A/D converter start request control register (TADCR) to 0).
and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with
interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the
timer A/D converter start request control register (TADCR) to 0).
3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D
converter start requests will not be issued.
* Do not set to 1 when complementary PWM mode is not selected.
Table 11.27 Setting of Transfer Timing by Bits BF1 and BF0
Bit 7
Bit 6
BF1 BF0 Description
0
0
Does not transfer data from the cycle set buffer register to the cycle
set register.
set register.
0
1
Transfers data from the cycle set buffer register to the cycle set
register at the crest of the TCNT_4 count.*
register at the crest of the TCNT_4 count.*
1
1
0
Transfers data from the cycle set buffer register to the cycle set
register at the trough of the TCNT_4 count.*
register at the trough of the TCNT_4 count.*
2
1
1
Transfers data from the cycle set buffer register to the cycle set
register at the crest and trough of the TCNT_4 count.*
register at the crest and trough of the TCNT_4 count.*
2
Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the
crest of the TCNT_4 count is reached in complementary PWM mode, when compare
match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or
when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or
normal operation mode.
match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or
when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or
normal operation mode.
2. These settings are prohibited when complementary PWM mode is not selected.