Renesas R5S72621 Manual Do Utilizador
Section 15 Serial Communication Interface with FIFO
Page 708 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFO-
data-full interrupt, and receive-error interrupts are requested independently.
When this module is not in use, it can be stopped by halting the clock supplied to it, saving
power.
In asynchronous mode, on-chip modem control functions (RTS and CTS) (SH7262: channel 1,
SH7264: channels 1 and 3).
The quantity of data in the transmit and receive FIFO data registers and the number of receive
errors of the receive data in the receive FIFO data register can be ascertained.
A time-out error (DR) can be detected when receiving in asynchronous mode.
In asynchronous mode, the base clock frequency can be either 16 or 8 times the bit rate.
When an internal clock is selected as a clock source and the SCK pin is used as an input pin in
In asynchronous mode, the base clock frequency can be either 16 or 8 times the bit rate.
When an internal clock is selected as a clock source and the SCK pin is used as an input pin in
asynchronous mode, either normal mode or double-speed mode can be selected for the baud
rate generator.
rate generator.