Renesas R5S72621 Manual Do Utilizador

 

 

Section 19   Serial I/O with FIFO 

 

 

Page 946 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

9 TXE 

0 R/W 

Transmit 

Enable 

0: Disables data transmission from the SIOFTxD pin 

1: Enables data transmission from the SIOFTxD pin 

  This bit setting becomes valid at the start of the next 

frame (at the rising edge of the SIOFSYNC signal). 

  When the 1 setting for this bit becomes valid, this 

module issues a transmit transfer request according 

to the setting of the TFWM bit in SIFCTR. When 

transmit data is stored in the transmit FIFO, 

transmission of data from the SIOFTxD pin begins. 

  This bit is initialized upon a transmit reset. 

8 RXE 

0 R/W 

Receive 

Enable 

0: Disables data reception from SIOFRxD 

1: Enables data reception from SIOFRxD 

  This bit setting becomes valid at the start of the next 

frame (at the rising edge of the SIOFSYNC signal). 

  When the 1 setting for this bit becomes valid, this 

module begins the reception of data from the 

SIOFRxD pin. When receive data is stored in the 

receive FIFO, a reception transfer request is issued 

according to the setting of the RFWM bit in SIFCTR. 

  This bit is initialized upon receive reset. 

7 to 2 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value should 
always be 0.