Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
Datasheet
105
DRAM Controller Registers (D0:F0)
5.2.7
C0DRA23—Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 20A–20Bh
Default Value:
0000h
Access:
RW/L
Size:
16 bits
See C0DRA01 register.
5.2.8
C0CYCTRKPCHG—Channel 0 CYCTRK PCHG
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 250–251h
Default Value:
0000h
Access:
RO, RW
Size:
16 bits
This is the Channel 0 CYCTRK Precharge registers.
Bit
Access
Default
Value
Description
15:8
RW/L
00h
Channel 0 DRAM Rank-3 Attributes (C0DRA3): This register defines DRAM
pagesize/number-of-banks for rank3 for given channel.
See table in register description for programming.
This register is locked by ME stolen Memory lock.
pagesize/number-of-banks for rank3 for given channel.
See table in register description for programming.
This register is locked by ME stolen Memory lock.
7:0
RW/L
00h
Channel 0 DRAM Rank-2 Attributes (C0DRA2): This register defines DRAM
pagesize/number-of-banks for rank2 for given channel.
See table in register description for programming.
This register is locked by ME stolen Memory lock.
pagesize/number-of-banks for rank2 for given channel.
See table in register description for programming.
This register is locked by ME stolen Memory lock.
Bit
Access
Default
Value
Description
15:11
RO
00000b Reserved
10:6
RW
00000b
Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the minimum
allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the
same rank-bank. This field corresponds to t
allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the
same rank-bank. This field corresponds to t
WR
in the DDR Specification.
5:2
RW
0000b
READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the minimum
allowed spacing (in DRAM clocks) between the READ and PRE commands to the
same rank-bank
allowed spacing (in DRAM clocks) between the READ and PRE commands to the
same rank-bank
1:0
RW
00b
PRE To PRE Delayed (C0sd_cr_pchg_pchg): This field indicates the
minimum allowed spacing (in DRAM clocks) between two PRE commands to the
same rank.
minimum allowed spacing (in DRAM clocks) between two PRE commands to the
same rank.