Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

Intel

Códigos do produto

P4X-UPE3210-316-6M1333

Datasheet

11

Figures

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3210 Chipset System Diagram Example............................................................. 16

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3200 Chipset System Diagram Example............................................................. 17

System Address Ranges............................................................................................ 37

DOS Legacy Address Range....................................................................................... 38

Main Memory Address Range ..................................................................................... 41

Pre-allocated Memory Example for 64 MB DRAM, 1 MB stolen and 1 MB TSEG .................. 42

PCI Memory Address Range ...................................................................................... 44

Conceptual Platform PCI Configuration Diagram ........................................................... 57

Memory Map to PCI Express Device Configuration Space ............................................... 60

10 MCH Configuration Cycle Flow Chart ........................................................................... 61
11 System Clocking Diagram ....................................................................................... 277
12 MCH Ballout Diagram (Top View Left – Columns 45–31) .............................................. 290
13 MCH Ballout Diagram (Top View Middle – Columns 30–16) .......................................... 291
14 MCH Ballout Diagram (Top View Left – Columns 15–1)................................................ 292
15 MCH Package Drawing ............................................................................................ 313
16 XOR Test Mode Initialization Cycles .......................................................................... 315

Tables

Intel Specification .................................................................................................... 19

Expansion Area Memory Segments ............................................................................. 39

Extended System BIOS Area Memory Segments........................................................... 39

System BIOS Area Memory Segments......................................................................... 40

Transaction Address Ranges – Compatible, High, and TSEG ........................................... 49

SMM Space Table ..................................................................................................... 50

SMM Control Table ................................................................................................... 51

DRAM Controller Register Address Map ....................................................................... 65

MCHBAR Register Address Map .................................................................................. 98

10 DRAM Rank Attribute Register Programming .............................................................. 104
11 EPBAR Address Map ............................................................................................... 141
12 Host-PCI Express Bridge Register Address Map (D1:F0) .............................................. 147
13 HECI Function in ME Subsystem (D3:F0) Register Address Map .................................... 193
14 KT IO/Memory Mapped Register Address Map ............................................................ 204
15 Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) ............................. 213
16 Direct Media Interface Register Address Map ............................................................. 259
17 Host Interface 4X, 2X, and 1X Signal Groups ............................................................. 268
18 Sample System Memory Dual Channel Symmetric Organization Mode ........................... 269
19 Sample System Memory Dual Channel Asymmetric Organization Mode with Intel

Flex Memory

Mode Enabled........................................................................................................ 270

20 Sample System Memory Dual Channel Asymmetric Organization Mode with Intel

Flex Memory

Mode Disabled ....................................................................................................... 270

21 Supported DIMM Module Configurations .................................................................... 271
22 Syndrome Bit Values .............................................................................................. 271
23 Absolute Minimum and Maximum Ratings.................................................................. 279
24 Current Consumption in S0 ..................................................................................... 281
25 Signal Groups........................................................................................................ 283
26 I/O Buffer Supply Voltage ....................................................................................... 285
27 DC Characteristics.................................................................................................. 286
28 MCH Ballout Sorted By Name................................................................................... 293
29 MCH Ballout Sorted By Ball...................................................................................... 303
30 XOR Chain 14 Functionality ..................................................................................... 316
31 XOR Chain Outputs ................................................................................................ 317
32 XOR Chain 0.......................................................................................................... 318
33 XOR Chain 1.......................................................................................................... 319