Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
122
Datasheet
5.2.30
C1ODTCTRL—Channel 1 ODT Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 69C–69Fh
Default Value:
00000000h
Access:
RO, RW
Size:
32 bits
This register provides ODT controls.
28:27
RO/P
00b
Error Rank Address (ERRRANK): Rank address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
00 = rank 0 (DIMM0)
01 = rank 1 (DIMM0)
10 = rank 2 (DIMM1)
11 = rank 3 (DIMM1)
memory of which an error (single bit or multi-bit error) has occurred.
00 = rank 0 (DIMM0)
01 = rank 1 (DIMM0)
10 = rank 2 (DIMM1)
11 = rank 3 (DIMM1)
26:24
RO
0h
Reserved
23:16
RO/P
00h
Error Syndrome (ERRSYND): Syndrome that describes the set of bits
associated with the first failing quadword.
associated with the first failing quadword.
15:2
RO
0h
Reserved
1
RO/P
0b
Multiple Bit Error Status (MERRSTS): This bit is set when an uncorrectable
multiple-bit error occurs on a memory read data transfer. When this bit is set,
the address that caused the error and the error syndrome are also logged and
they are locked until this bit is cleared. This bit is cleared when it receives an
indication that the processor has cleared the corresponding bit in the ERRSTS
register.
multiple-bit error occurs on a memory read data transfer. When this bit is set,
the address that caused the error and the error syndrome are also logged and
they are locked until this bit is cleared. This bit is cleared when it receives an
indication that the processor has cleared the corresponding bit in the ERRSTS
register.
0
RO/P
0b
Correctable Error Status (CERRSTS): This bit is set when a correctable
single-bit error occurs on a memory read data transfer. When this bit is set, the
address that caused the error and the error syndrome are also logged and they
are locked to further single bit errors, until this bit is cleared. But, a multiple bit
error that occurs after this bit is set will over-write the address/error syndrome
info. This bit is cleared when it receives an indication that the processor has
cleared the corresponding bit in the ERRSTS register.
single-bit error occurs on a memory read data transfer. When this bit is set, the
address that caused the error and the error syndrome are also logged and they
are locked to further single bit errors, until this bit is cleared. But, a multiple bit
error that occurs after this bit is set will over-write the address/error syndrome
info. This bit is cleared when it receives an indication that the processor has
cleared the corresponding bit in the ERRSTS register.
Bit
Access
Default
Value
Description
Bit
Access
Default
Value
Description
31:12
RO
00000h Reserved
11:8
RW
0h
DRAM ODT for Read Commands (sd1_cr_odt_duration_rd): Specifies the
duration in MDCLKs to assert DRAM ODT for Read Commands. The Async value
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
duration in MDCLKs to assert DRAM ODT for Read Commands. The Async value
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
7:4
RW
0h
DRAM ODT for Write Commands (sd1_cr_odt_duration_wr): Specifies the
duration in MDCLKs to assert DRAM ODT for Write Commands. The Async value
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
duration in MDCLKs to assert DRAM ODT for Write Commands. The Async value
should be used when the Dynamic Powerdown bit is set. Else use the Sync value.
3:0
RW
0h
MCH ODT for Read Commands (sd1_cr_mchodt_duration): Specifies the
duration in MDCLKs to assert MCH ODT for Read Commands
duration in MDCLKs to assert MCH ODT for Read Commands