Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

Datasheet

147

Device 1 contains the controls associated with the PCI Express root port that is the 

intended attach point for external devices. In addition, it also functions as the virtual 

PCI-to-PCI bridge. The table below provides an address map of the D1:F0 registers 

listed by address offset in ascending order. This chapter provides a detailed bit 

description of the registers.

When reading the PCI Express "conceptual" registers such as this, you may not get a 

valid value unless the register value is stable.

The PCI Express* Specification defines two types of reserved bits: 

Reserved and Preserved:

• Reserved for future RW implementations; software must preserve value read for 

writes to bits.

• Reserved and Zero: Reserved for future R/WC/S implementations; software must 

use 0 for writes to bits.

Unless explicitly documented as Reserved and Zero, all bits marked as reserved are 

part of the Reserved and Preserved type, which have historically been the typical 

definition for Reserved.

Most (if not all) control bits in this device cannot be modified unless the link is down. 

Software is required to first disable the link, then program the registers, and then re-

enable the link (which will cause a full-retrain with the new settings).

0–1h

VID1

Vendor Identification

8086h

RO 

2–3h

DID1

Device Identification

29F1h

RO 

4–5h

PCICMD1

PCI Command

0000h

RO, RW 

6–7h

PCISTS1

PCI Status

0010h

RO, RWC 

8h

RID1

Revision Identification

see register 

description

RO 

9–Bh

CC1

Class Code

060400h

RO 

Ch

CL1

Cache Line Size

00h

RW 

Eh

HDR1

Header Type

01h

RO 

18h

PBUSN1

Primary Bus Number

00h

RO 

19h

SBUSN1

Secondary Bus Number

00h

RW 

1Ah

SUBUSN1

Subordinate Bus Number

00h

RW 

1Ch

IOBASE1

I/O Base Address

F0h

RO, RW 

1Dh

IOLIMIT1

I/O Limit Address

00h

RW, RO 

1E–1Fh

SSTS1

Secondary Status

0000h

RO, RWC