Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
Intel Manageability Engine Subsystem PCI (D3:F0,F3)
208
Datasheet
7.2.7
KTFCR—KT FIFO Control
B/D/F/Type:
0/3/3/KT MM/IO
Address Offset: 2h
Default Value:
00h
Access:
WO
Size:
8 bits
When Host writes to this address, it writes to the KTFCR. The FIFO control Register of
the serial interface is used to enable the FIFO's, set the receiver FIFO trigger level and
clear FIFO's under the direction of the Host.
When Host reads from this address, it reads the KTIIR.
Note:
Reset: Host System Reset or D3->D0 transition.
Bit
Access
Default
Value
Description
7:6
WO
00b
Receiver Trigger Level (RTL): Trigger level in bytes for the RCV FIFO. Once
the trigger level number of bytes is reached, an interrupt is sent to the Host.
00 = 01
01 = 04
10 = 08
11 = 14
the trigger level number of bytes is reached, an interrupt is sent to the Host.
00 = 01
01 = 04
10 = 08
11 = 14
5:4
WO
00b
Reserved
3
WO
0b
RDY Mode (RDYM): This bit has no affect on hardware performance.
2
WO
0b
XMT FIFO Clear (XFIC): When the Host writes one to this bit, the hardware
will clear the XMT FIFO. This bit is self-cleared by hardware.
will clear the XMT FIFO. This bit is self-cleared by hardware.
1
WO
0b
RCV FIFO Clear (RFIC): When the Host writes one to this bit the hardware will
clear the RCV FIFO. This bit is self-cleared by hardware.
clear the RCV FIFO. This bit is self-cleared by hardware.
0
WO
0b
FIFO Enable (FIE): When set, this bit indicates that the KT interface is working
in FIFO node. When this bit value is changed, the RCV and XMT FIFO are cleared
by hardware.
in FIFO node. When this bit value is changed, the RCV and XMT FIFO are cleared
by hardware.