Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados
Códigos do produto
P4X-UPE3210-316-6M1333
Introduction
22
Datasheet
1.2.4
PCI Express* Interface
The 3210 MCH supports either two PCI Express* 8-lane (x8) ports or one PCI Express
16-lane (x16) port.
PCI Express 16-lane (x16) port is not shown in figure). The 3200 MCH supports one 8-
). The 3200/3210 MCHs do not support PCI
Express graphics. The PCI Express ports are intended for external device attach. The
PCI Express ports are compliant to the PCI Express* Base Specification revision 1.1.
The x8 ports operate at a frequency of 2.5 Gb/s on each lane while employing 8b/10b
encoding, and support a maximum theoretical bandwidth of 4.0 GB/s in each direction.
The PCI Express interface includes:
• For the 3210 MCH, either two 8-lane PCI Express ports or one 16-lane PCI Express
port, compatible to the PCI Express* Base Specification, Revision 1.1.
• For the 3200 MCH, one 8-lane PCI Express port, compatible to the PCI Express*
Base Specification, Revision 1.1
• PCI Express frequency of 1.25 GHz resulting in 2.5 Gb/s each direction per lane.
• Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of
• Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface
• Maximum theoretical realized bandwidth on the interface of 4 GB/s in each
direction simultaneously, for an aggregate of 8 GB/s when x16.
• PCI Express Enhanced Addressing Mechanism allows for accessing the device
configuration space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
Hierarchical PCI-compliant configuration mechanism for downstream devices
(i.e., normal PCI 2.3 Configuration space as a PCI-to-PCI bridge).
• Supports “static” lane numbering reversal. This method of lane reversal is
controlled by a Hardware Reset strap, and reverses both the receivers and
transmitters for all lanes (e.g., TX[15]->TX[0], RX[15]->RX[0]). This method is
transparent to all external devices and is different than lane reversal as defined in
the PCI Express Specification. In particular, link initialization is not affected by
static lane reversal.