Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Ficha De Dados

264

Datasheet

B/D/F/Type:

0/0/0/DMIBAR

Address Offset: 20–23h

Default Value:

01000000h

Access:

RW, RO 

Size:

32 bits

This register controls the resources associated with PCI Express Virtual Channel 1.

31

RW

0b

Virtual Channel 1 Enable (VC1E): 
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled. 

30:27

RO

0h

Reserved 

26:24

RW

001b

Virtual Channel 1 ID (VC1ID): This field assigns a VC ID to the VC resource. 
Assigned value must be non-zero. This field can not be modified when the VC is 
already enabled.

23:20

RO

0h

Reserved 

19:17

RW

000b

Port Arbitration Select (PAS): This field configures the VC resource to 
provide a particular Port Arbitration service. Valid value for this field is a number 
corresponding to one of the asserted bits in the Port Arbitration Capability field 
of the VC resource.

16:8

RO

000h

Reserved 

7:1

RW

00h

Traffic Class / Virtual Channel 1 Map (TCVC1M): This field indicates the TCs 
(Traffic Classes) that are mapped to the VC resource. Bit locations within this 
field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. 
When more than one bit in this field is set, it indicates that multiple TCs are 
mapped to the VC resource. To remove one or more TCs from the TC/VC Map of 
an enabled VC, software must ensure that no new or outstanding transactions 
with the TC labels are targeted at the given Link.

0

RO

0b

Traffic Class 0 / Virtual Channel 1 Map (TC0VC1M): Traffic Class 0 is 
always routed to VC0.